AITEC Contract Research Projects in FY1995 : Abstract

(22) A Parallel Computing Silicon Compiler for Low Power LSI Design

Dr. Kazuo Taki, Professor, Kobe University


A STUDY ON LOW-POWER VLSI SILICON COMPILER WITH PARALLEL COMPUTATION


This study aims at developing the world's first silicon compiler for low-power VLSI design, which integrates low-power logic synthesis and low-power layout. KL1 and parallel object-oriented programming techniques will be used for software design and implementations. A new technology, pass-transistor logic, will be a synthesizing target, which will achieve quite lower power dissipation than ever. This study thus aims at achieving completely new functions with high-speed parallel processing.


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