(65) Experimental Parallel Hierarchical Recursive Layout System: Co-HLEX

	Machine:     Multi-PSI, PIM
	Environment: PIMOS
	Language:    KL1
	Source Code: 3.5 MB
	Documents:   None

Overview

Co-HLEX generates a layout diagram of a given circuit under a prespecified planned chip shape and a set of module proximity conditions. Bipolar analog circuit is the current repertoire.

Configuration

Function

The motivation of Co-HLEX development includes; the search for a new parallel layout algorithm, the representation power proof of KL1, and the problem solving power proof of parallel inference machines, Multi-PSI and PIM. The original flat circuit net data input is transformed into a hierarchical process network named CMPN. Then a hierarchical recursive concurrent theorem proving algorithm named HRCTL is applied to CMPN to generate a layout under the given planned chip shape. Due to the runtime co-operations among CMPN nodes running in parallel, module shape and wire abutments could newly be realized.

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