ABSTRACT 

An LSI is designed using a combination of register transfer level descrip-
tion,gate level description and behavior description. The logic synthesis and 
the layout-wiring have been largely automated. However,even now,high level 
synthesis is not available.Our study has focused on high level synthesis. 

HIGH LEVEL SYNTHESIS 

Behavior description is parsed and developed to Binomials. 

Initial schedule table is generated from Binomials. This is a data form 
that corresponds to one datapath circuit and is possible to optimize. 

Optimum schedule table is generated by Parallel RA optimizing. 

Variables are allocated to registers based on the lifetime of the variables. 

RT level description is generated in the Hardware Description Language. 
It expresses both datapath and micro instruction code. 





LSI Design Process



High Level Synthesis Process


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